Random-access memory (RAM; /ram/) is a form of computer memory that can be read and changed in any order, typically used to store working data and machine code. A random-access memory device allows data items to be read or written in almost the same amount of time irrespective of the physical location of data inside the memory, in contrast with other direct-access data storage media (such as hard disks, CD-RWs, DVD-RWs and the older magnetic tapes and drum memory), where the time required to read and write data items varies significantly depending on their physical locations on the recording medium, due to mechanical limitations such as media rotation speeds and arm movement.
Random-access memory (RAM) is volatile, which means that it requires power to maintain the stored information when it is not being written to. Therefore, RAM requires circuitry to control the flow of data in and out of the memory storage. RAM is typically associated with dynamic random-access memory (DRAM). Static random-access memory (SRAM) is a subset of R-A-M which acts as a type of cache for R-A-M.
In most modern computers and many external devices, SRAM takes the form of integrated circuit chips. Electrical charge stored in a capacitor represents binary information stored in the device. The charge flows into or out of the capacitor as required by the controlling logic. In most types of R-A-M, this logic is contained within a dedicated memory controller chip. SRAM is used as internal cache, often leading to it being generically referred to as a cache or a memory buffer.
Computer systems with microprocessors use a specialized piece of hardware to perform input and output operations with SRAM. This device is known as a bus controller or bus bridge.
SRAM is also available in many forms for embedded electronics applications, where it may be used as either main memory or cache memory. With regard to special memory architectures, SRAM can be classified into single-ported memory, dual-ported memory, and quad-ported memory.
Single-ported SRAM is typically implemented as a type of “leaky” bucket brigade device with one serial access port. It was the original form of SRAM.
Dual-ported SRAM is a computer chip most commonly composed of two independent sections, each with its own address and data buses, to allow two separate devices or subsystems to share the same physical random access memory (RAM) chip.
A quad-ported memory chip has four independent parallel data and address buses, allowing more than two devices to share the same SRAM chip. SRAM is also used as a form of main memory, although its cost per bit of capacity makes it unsuitable for modern large-scale application such as storing all of a computer’s software or operating system. SRAM is therefore considered to be best suited for applications requiring high latency, typically less than one second, such as background functions and special purpose applications.
Contents [hide] 1 History 2 Form factors 3 Paradigm shift: From sequential access to random access 4 Contents 4.1 Data and address blocks 4.2 Operating modes 4.3 Single-ported vs. dual-ported 4.4 Quad-port 4.5 Passive quad-port 4.6 Alternative single-port SRAM 4.7 Embedded SRAM 5 Benchmarking 6 See also 7 References 8 External links 8.1 Datasheets
The original form of SRAM was introduced with the IBM 7070 in 1967, and is now known as Single Port Memory, or SP-RAM. It found frequent use in embedded applications, due to the low cost and simplicity of its data paths and because it did not require refresh. It was also used in many early minicomputers used to control hardware such as disk drives and printers.
The dual-ported SRAM pioneered by the Intel 4004 (1971) was quickly adapted into this new category of memory, and is still used today. Quad-ported SRAM was first designed around the Intel 8080; by the mid-1970s, several manufacturers were offering this form of computer memory. Quad-ported SRAM was a major improvement over dual-ported SRAM, as it did not require the refresh of all four ports during a write access.
Paradigm shift: From sequential access to random access 
In the early 1970s, RAM had become inexpensive enough that it was directly integrated into the logic of other devices as an embedded system, rather than used as a peripheral. In order to maximize their own use of RAM, embedded systems started using multiplexers to share the RAM among several peripheral devices. In fact, because of this concurrent access by many devices, embedded systems required faster RAM than what was available at that time. To solve this problem, memory manufacturers developed SRAM, which was essentially the same as the B- and C-types of DRAM, but not requiring refresh.
As SRAM memory developed for such purposes, it was also used as a form of cache memory between a processor and slower memory such as disk drives or network interface controllers (NICs). Because SRAM is much faster than regular DRAM but does not support burst accesses like DRAM does, it is well suited for this use.
To take maximum advantage of SRAM’s properties and minimize its disadvantages, its use was nearly always accompanied by a CPU cache that acted as an intermediate step between the CPU and main system RAM. The cache would hold the most recently used data and instructions, and when a program needed data not currently in the cache, the CPU could request it from the RAM.
Main article: Memory cell
SRAM is a form of memory that retains its contents as long as power is being supplied. SRAM stores each bit of data in a separate capacitor within an integrated circuit. Hence, unlike DRAM, SRAM does not need to be constantly refreshed. This allows SRAM to have a much smaller footprint and consume much less power than DRAM. Although SRAM can be slower than DRAM due to its higher access time, newer technologies have significantly reduced this penalty.
Typical SRAM memory cells are made up of two transistors connected in series, with an additional transistor connected in parallel. The cell’s logic circuit can control the charge in the capacitor either positively or negatively. When the voltage on the output is zero, no current can flow out of the capacitor.
Data and address blocks 
The data block is where data resides in a known location within memory. The cell’s control circuit signals when power has been removed (grounding), allowing for reading or writing of data (a write only cell). The amount of time that power must be removed to change data-holding capacitors is referred to as refresh cycle time (RCT).
The address block contains data addresses, which are used to store data in memory. The logic circuit signals the address when power is removed (grounding), so that the CPU can access the indicated address. The amount of time that power must be removed before updating data-holding capacitors is called an access time (AT).
Single-ported vs. dual-ported 
While SRAM has no requirement for refresh or any other form of refresh cycle, it is possible to use multiple ports for each bit, allowing each port to have its own independent refresh cycle. This is called dual-ported SRAM.
Quad-port SRAM is very similar to dual-ported SRAM, but has four ports for each bit instead of two. This allows each port to have its own refresh cycle, independently of the other ports. Although quad-ported SRAM was initially seen as a higher performance form of memory compared to single ported SRAM, this has proven not to be the case.
Operating modes 
SRAM can be implemented in several different ways, using different technologies and addressing methods. All implementations are designed to store one bit in each capacitor; however, the number of data bits stored within the same IC varies.
Single-port SRAM, also known as single-port dynamic RAM (SP-DRAM), is used in the MOS Technology 4066/2, while dual-ported SP-DRAM was used in the MOS Technology 86C50. Both microprocessors have 1 KB of memory each.
Quad-port SRAM was first implemented by Fujitsu in 1989 with its family of SCM1408 random access memories, which consisted of two 16 KB caches connected by a 32 bit bus. Fujitsu’s quad-port random access memory differed from others in that it was not available during operation for “hot swapping”, but only when the system was powered off.  
Multi-port SRAM, also known as multi-port DRAM, was first implemented by Fujitsu in a 64 KB dual-port random access memory in 1989.  This was followed by a 16 KB dual-port random access memory in 1991. 
This was followed by a 16 KB dual-port random access memory in 1991. In 1998, NEC released its family of SCM1608/6400 memories that consisted of six 4 KB double data rate (DDR) caches interconnected via 32 bit link and two 16 bit buses. Sony used this chip for its PlayStation 2 video game console.